Use of current-mode logic (“CML”) technology is becoming increasingly popular for high-speed communication, especially point-to-point communication. CML is especially attractive in applications with communication rates equal to or in excess of a gigabit per second. However, CML interfaces heretofore have had dedicated data paths. For example, a CML interface conventionally includes a plurality of cells. Of those cells, each cell included dedicated circuitry, where some of the cells were receivers and others of the cells were transmitters. Thus, each cell of a CML interface was either a transmitter-only cell or a receiver-only cell as determined by the manufacturer of the integrated circuit containing such cells. However, this inflexibility not only imposes application design constraints, it further requires dedicated phase locking circuitry, such as a phase-locked loop (“PLL”) for each of the cells. Thus, if there were 64 cells, there would be 64 or more separate PLLs.
Accordingly, it would be both desirable and useful to provide an interface cell that overcomes one or more of the above-mentioned limitations associated with prior interface cells.